The present invention relates to a non-volatile semiconductor memory device, and more particularly to an erasable programmable read-only memory.
An erasable programmable read-only memory (referred to as "EPROM" hereinafter) has been proposed in which each memory cell transistor has a "double-gate structure" of a floating gate and a control gate, which are formed above a channel region in a lateral side-by-side relation. In this type of EPROM, it has been proposed to access the memory by reversing the functions of the source and drain of two diffusion layers of each memory cell between a data write mode and a data read mode. More specifically, the first diffusion layer serving as the drain in data write mode is used as the source in the data read mode, while the second diffusion layer serving as the source in the data write mode is used as the drain in the data read mode. In accessing the memory cell, the data read/write efficiency can be improved and occurrence of malfunctions can be suppressed by reversing the functions of the source and drain of a cell transistor between the data read and write modes.
With the use of such an accessing technique, however, neither one of the two diffusion layers of each cell transistor can be coupled to a common wiring line. This enforces the utilization of the "double-bit line structure" in an EPROM that has two diffusion layers of each cell transistor coupled to independent bit lines. In this case, contact holes need to be provided separately for two diffusion layers of each cell and these diffusion layers should be coupled through the contact holes to the first and second bit lines that are separately running on a chip substrate. This results in a difficulty in designing the optimum wiring pattern for the memory cells on the substrate as well as an undesirable increase in the cell area. The complexed wiring pattern deteriorates the accessing speed of the EPROM.